//Listing 8.5
module uart_test
   (
    input wire clk, reset,
    input wire rx,
    input wire btn,
    output wire tx
  
   );

   // signal declaration
   wire tx_full, rx_empty, btn_tick,rx_done_tick;
   wire [7:0] rec_data, rec_data1;

   // body
   // instantiate uart
   uart uart_unit
      (.clk(clk), .reset(reset), .rd_uart(rx_done_tick),
       .wr_uart(rx_done_tick), .rx(rx), .w_data(rec_data1),
       .tx_full(tx_full), .rx_empty(rx_empty),
       .r_data(rec_data), .tx(tx), .rx_done_tick(rx_done_tick));
   // instantiate debounce circuit
   //debounce btn_db_unit
     // (.clk(clk), .reset(reset), .sw(rx_done_tick),
       //.db_level(), .db_tick(btn_tick));
   // incremented data loops back
   //assign rec_data1 = rec_data + 1;
	//assign rec_data1 = rec_data;
   


endmodule